The XinDA team has a combined 80 years experience in helping customers tape-out with timing, power and signal integrity. We look forward to be a partner in your upcoming design challenges.
Ken Tseng founded XinDA in 2018 and has served as CEO. Prior to XinDA, he was Distinguished Engineer and Group Director at Cadence Design Systems, co-founder and CTO of Altos Design Automation, and General Manager of Altos Beijing where he pioneered the Liberate suite of fast library characterization tools, a key enabler for low voltage design. Prior to Altos, Ken invented CeltIC the premier tool for signal integrity analysis. He holds more than 15 patents and publications in timing, noise and power analysis and characterization, and has over 30 years experience in EDA and semiconductor industries.
Ken received the BS and MS degrees in electrical engineering from the University of Texas at Austin, and conducted graduate research in crosstalk timing analysis at Stanford University.
Dr. Danny Li is founder and CTO of XinDA. Prior to that, he worked for Cadence as Sr. Principle Software Engineer since 2015, during which he specialized in fast and scalable transistor-level algorithms. He was the key developer for Liberate AMS, a highly efficient characterization tool for custom and mixed-signal ICs. He also holds a patent on satisfiability-based transistor-level logic analysis.
Danny received his PhD degree in Electronic Systems from Royal Institute of Technology (KTH), Stockholm, Sweden. His research topics include logic synthesis, binary sequences, and built-in self test (BIST). He published over 15 papers in major conferences and journals. Danny got his MS degree in SoC Design also from KTH Sweden, and BS degree in Microelectronics from Fudan University, Shanghai, China.
Danny has a special interest in algorithm design, C++ language standard, and redstone contraptions in Minecraft.
Ting-Hau Hsiao is VP of XinDA. Before joining XinDA, he was Senior Staff at Synopsys where he pioneered advanced statistical models for SiliconSmart LVF characterization. At Cadence, Ting was Senior Software Manager who built Taiwan R&D team from the ground up, played a key role in Liberate standard cell and memory LVF characterization, and drove their successful adoption at a leading foundry. Ting also worked for TSMC, where he was the author of the patented EagleEye, one of the first programmable application rule checker that verifies the correctness of SoC IP library. Ting earned multiple awards for his outstanding contributions during his 15 years of R&D and management experience in the semiconductor and EDA industries.
Ting received his Master degree in Electrical Engineering from National Cheng Kung University.
Kevin Chou serves on XinDA’s business advisor panel. Prior to XinDA, he was Group Director at Synopsys, where he was responsible for both P&L and technology development direction for the SiliconSmart tool suite, significantly increasing run rate at all leading foundries and IP providers. Prior to Synopsys, Kevin was Design Engineering Group Director at Cadence Design Systems, co-founder and VP of R&D at Altos Design Automation where he led international R&D teams and delivered the Liberate/Variety/LV/MX tool suite, key enablers for mobile and lower power designs. Prior to Altos, Kevin invented makeCdB, the first commercial transistor level signal integrity library, critical enabler to CeltIC’s industry wide adoption.
Kevin received a BSEE from The Cooper Union and a MSEE from Stanford University. He holds three patents in characterization and verification, and a publication in noise analysis.